By Marco Annaratone (auth.)
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Additional resources for Digital CMOS Circuit Design
Polysilicon drafn substrate T Cdb Figure 2-9: MaS transistor parasitic capacitances. Fig. 2-9 shows a cross-section of a transistor with its associated parasitic capacitances. Covl is the overlap capacitance between gate and either source or drain. Csub accounts for the charge (or lack thereof) under the gate, while Cdb and Csb are the drain and source junction capacitances. The capacitances between the four terminals of the MaS transistor are shown in Fig. 2-10, where CSUb is represented by two capacitances Cgs and Cgd associated with source and drain, respectively.
0 Vin (V) Figure 2-20: Inverter voltage transfer function using the Brews model. temporal information is contained in Fig. 2-20. 5 and in this section is only the DC analysis of the CMOS inverter. Delay has not been discussed yet and will be dealt with in Chapter 5. Eq. (2-18) has also been used to detennine the drain current of the CMOS inverter for the same pull-uPlpull-down ratios of Fig. 2-20; the results are shown in Fig. 2-21. From a qualitative point of view, the shape of the curve was expected.
An interesting characteristic of these curves is their sharp transition: this is a peculiar feature of CMOS technology. The sharpness of the transition is due to the fact that having both devices in saturation is a very unstable configuration, because the two transistors, acting as current generators, are in series. A very small increase - or decrease - in input voltage causes a drastic change in O:Itput voltage. Moreover, the sharpness of the transition does not depend on the pull-up/pull-down ratio, as is the case with an nMOS inverter with depletion load.