Download Design-for-Test and Test Optimization Techniques for by Brandon Noia, Krishnendu Chakrabarty PDF

By Brandon Noia, Krishnendu Chakrabarty

This booklet describes cutting edge recommendations to handle the trying out wishes of 3D stacked built-in circuits (ICs) that make the most of through-silicon-vias (TSVs) as vertical interconnects. The authors establish the most important demanding situations dealing with 3D IC trying out and current effects that experience emerged from state-of-the-art study during this area. assurance contains subject matters starting from die-level wrappers, self-test circuits, and TSV probing to test-architecture layout, try out scheduling, and optimization. Readers will take advantage of an in-depth examine test-technology strategies which are had to make 3D ICs a fact and commercially possible.

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Extra resources for Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

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5 examines three different stacked memories with varying test, repair, and redundancy strategies and their impact on stack yield and cost. 6 concludes this chapter. 1 Wafer Stacking Methodologies The stacking of dies to create a 3D SIC can generally occur in one of three ways— wafer-to-wafer (W2W) stacking, die-to-wafer (D2W) stacking, or die-to-die (D2D) B. Noia and K. 1007/978-3-319-02378-6__2, © Springer International Publishing Switzerland 2014 11 12 2 Wafer Stacking and 3D Memory Test stacking.

BP processes result in larger compound yield improvements than FIFOn and FIFO1 processes. Utilizing different matching criterion depending on wafer yields can further improve stack yields. • FIFO1 and FIFOn processes are both prone to repository pollution as the stack production size increases, effectively reducing compound yield over time. 4 Fault Modeling of TSV Resistive-Opens in Stacked DRAM In a memory stack similar to that shown in Fig. 4, TSVs make up the wordlines and bitlines for accessing data in each DRAM cell on a memory array die and route data to and from the peripheral logic on a logic die.

4, the peripheral logic, memory controllers, and logic cores all belong to the bottom logic die while the other two dies contain DRAM memory arrays. TSVs act as bitlines and wordlines to connect the array cells to the periphery logic on the bottom die. Decoders and multiplexers can be added to the memory array dies to share a single TSV between multiple wordlines and to select one of several bitlines to connect to a peripheral sense amplifier. Similar designs have been proposed in the literature [68, 69], and Tezzaron Semiconductor has manufactured such designs in silicon [70].

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