By R. Jacob Baker
Chapter 1 creation to CMOS layout (pages 1–30):
Chapter 2 The good (pages 31–58):
Chapter three The steel Layers (pages 59–82):
Chapter four The lively and Poly Layers (pages 83–104):
Chapter five Resistors, Capacitors, MOSFETs (pages 105–130):
Chapter 6 MOSFET Operation (pages 131–160):
Chapter 7 CMOS Fabrication (pages 161–212):
Chapter eight electric Noise: an summary (pages 213–268):
Chapter nine versions for Analog layout (pages 269–310):
Chapter 10 types for electronic layout (pages 311–330):
Chapter eleven The Inverter (pages 331–352):
Chapter 12 Static good judgment Gates (pages 353–374):
Chapter thirteen Clocked Circuits (pages 375–396):
Chapter 14 Dynamic common sense Gates (pages 397–410):
Chapter 15 VLSI format Examples (pages 411–432):
Chapter sixteen reminiscence Circuits (pages 433–482):
Chapter 17 Sensing utilizing ?? Modulation (pages 483–522):
Chapter 18 designated objective CMOS Circuits (pages 523–550):
Chapter 19 electronic Phase?Locked Loops (pages 551–612):
Chapter 20 present Mirrors (pages 613–656):
Chapter 21 Amplifiers (pages 657–710):
Chapter 22 Differential Amplifiers (pages 711–744):
Chapter 23 Voltage References (pages 745–772):
Chapter 24 Operational Amplifiers I (pages 773–828):
Chapter 25 Dynamic Analog Circuits (pages 829–862):
Chapter 26 Operational Amplifiers II (pages 863–908):
Chapter 27 Nonlinear Analog Circuits (pages 909–930):
Chapter 28 facts Converter basics (pages 931–964):
Chapter 29 info Converter Architectures (pages 965–1022):
Chapter 30 enforcing info Converters (pages 1023–1098):
Chapter 31 suggestions Amplifiers (pages 1099–1156):
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Additional resources for CMOS: Circuit Design, Layout, and Simulation, Third Edition
John-Wiley and Sons, 2009. ISBN 978-0470290262  S. M. Sandier and C. Hymowitz, SPICE Circuit Handbook, McGraw-Hill, 2006. ISBN 978-0071468572  K. Kundert, The Designer's Guide to SPICE and Spectre, Springer, 1995. ISBN 978-0792395713  A. Vladimirescu, The SPICE Book, John-Wiley and Sons, 1994. ISBN 9780471609261  F. M. Wanlass, "Low Standby-Power Complementary Field Effect Transistor," US Patent 3,356,858, filed June 18, 1963, and issued December 5, 1967. 1 What would happen to the transfer function analysis results for the circuit in Fig.
This can be the result of trade-offs made between cost and performance, changes in the marketability of the chip, or simply changes in the customer's needs. In almost all cases, major changes after the chip has gone into production are not possible. This text concentrates on custom IC design. Other (noncustom) methods of designing chips, including field-programmable-gate-arrays (FPGAs) and standard cell libraries, are used when low volume and quick design turnaround are important. Most chips that are mass produced, including microprocessors and memory, are examples of chips that are custom designed.
For production purposes, each die on a wafer is usually identical, as seen in the photograph in Fig. 2. Added to the wafer are test structures and process monitor plugs (sections of the wafer used to monitor process parameters). The most common wafer size (diameter) in production at the time of this writing is 300 mm (12 inch). A die fabricated with other dice on the silicon wafer > D Top (layout) view 1 Wafer diameter is typically 100 to 300 mm. 2 CMOS integrated circuits are fabricated on and in a silicon wafer.