By Liqiang He, Cha Narisu (auth.), Yong Dou, Ralf Gruber, Josef M. Joller (eds.)
This booklet constitutes the refereed complaints of the eighth foreign Workshop on complex Parallel Processing applied sciences, APPT 2009, held in Rapperswil, Switzerland, in August 2009.
The 36 revised complete papers awarded have been rigorously reviewed and chosen from seventy six submissions. All present elements in parallel and disbursed computing are addressed starting from and software program concerns to algorithmic elements and complicated functions. The papers are geared up in topical sections on structure, graphical processing unit, grid, grid scheduling, cellular program, parallel program, parallel libraries and performance.
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Extra resources for Advanced Parallel Processing Technologies: 8th International Symposium, APPT 2009, Rapperswil, Switzerland, August 24-25, 2009 Proceedings
339–351 (2006) 25. : Using destinationset prediction to improve the latency/bandwidth tradeoﬀ in shared-memory multiprocessors. In: 30th Int’l. Symp. on Computer Architecture (ISCA), June 2003, pp. 206–217 (2003) 26. : An adaptive cache coherence protocol optimized for producer-consumer sharing. In: 13th Int’l. Symp. on High-Performance Computer Architecture (HPCA), February 2007, pp. cn Abstract. The large working sets of commercial and scientiﬁc workloads favor a shared L2 cache design that maximizes the aggregate cache capacity and minimizes oﬀ-chip memory requests in Chip Multiprocessors (CMP).
Symp. on Computer Architecture (ISCA), May 1988, pp. 280–289 (1988) 9. : LimitLESS directories: A scalable cache coherence scheme. In: 4th Int. Conf. on Architectural Support for Programming Language and Operating Systems (ASPLOS), April 1991, pp. 224–234 (1991) 10. : Reducing memory traﬃc requirements for scalable directory-based cache coherence schemes. In: Int’l. Conference on Parallel Processing (ICPP), August 1990, pp. 312–321 (1990) 11. : Improving multiple-cmp systems using token coherence.
This paper studies the directory structure of shared L2 cache design in CMP. In CMP, directory is stored in L2 cache, and implies the similar problem as CCNUMA: memory overhead and long miss latencies. But the directory capacity and the directory access latency have signiﬁcantly diﬀerence between CMP and CC-NUMA. The directory capacity of CMP is much smaller than that of CCNUMA, but it will consume the constrained on-chip resource. The directory access latency of CMP is much lower than that of CC-NUMA, but the directory accesses are more frequent than that in CC-NUMA due to diﬀerent L2 cache design.