By Banqiu Wu, Ajay Kumar, Sesh Ramaswami
The newest advances in three-d built-in circuit stacking technology
With a spotlight on commercial purposes, 3D IC Stacking Technology bargains entire insurance of layout, try out, and fabrication processing equipment for three-d gadget integration. every one bankruptcy during this authoritative advisor is written via specialists and information a separate fabrication step. destiny purposes and state of the art layout power also are mentioned. this is often a necessary source for semiconductor engineers and conveyable gadget designers.
3D IC Stacking Technology covers:
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Extra resources for 3D IC Stacking Technology
14 Die-to-substrate or die-to-die flow. The choice of fabrication and assembly flow must also consider handoff points between the suppliers in the manufacturing chain. For via-middle TSS, the foundry will be responsible for formation of the TSV, since contamination control prohibits wafers from being removed from the wafer fab, processed externally, and then returned to the fab. Either the foundry or an outsourced assembly and test (OSAT) provider might perform the PFWP operations. Logistical and technical considerations such as thin-wafer handling, testability/known good die, and liability ownership are factors to consider in selecting the combination of flow and handoff point.
All rights reserved. Except as permitted under the United States Copyright Act of 1976, no part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written permission of the publisher. ISBN 978-0-07-174196-5 MHID 0-07-174196-8 The material in this eBook also appears in the print version of this title: ISBN 978-0-07-174195-8, MHID 0-07-174195-X. All trademarks are trademarks of their respective owners. Rather than put a trademark symbol after every occurrence of a trademarked name, we use names in an editorial fashion only, and to the benefit of the trademark owner, with no intention of infringement of the trademark.
All of these 3D configurations can suffer from chip-to-chip interconnect bottlenecks due to wirebond or solder ball density limitations. Another possible configuration for stacked SiPs, which is the topic of this book, utilizes TSVs instead of wirebonds to connect between tiers in the 3D stack. 3 shows a cross-sectional view of a 3D SiP utilizing through silicon vias and Fig. 4 shows a 3D x-ray image of the structure. The processing techniques for forming TSVs will be described in detail in later chapters of this book.